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Espressif Systems /ESP32-C3 /APB_SARADC /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SARADC_START_FORCE)SARADC_START_FORCE 0 (SARADC_START)SARADC_START 0 (SARADC_SAR_CLK_GATED)SARADC_SAR_CLK_GATED 0SARADC_SAR_CLK_DIV 0SARADC_SAR_PATT_LEN 0 (SARADC_SAR_PATT_P_CLEAR)SARADC_SAR_PATT_P_CLEAR 0SARADC_XPD_SAR_FORCE 0SARADC_WAIT_ARB_CYCLE

Description

digital saradc configure register

Fields

SARADC_START_FORCE

select software enable saradc sample
SARADC_START

software enable saradc sample
SARADC_SAR_CLK_GATED

SAR clock gated
SARADC_SAR_CLK_DIV

SAR clock divider
SARADC_SAR_PATT_LEN

0 ~ 15 means length 1 ~ 16
SARADC_SAR_PATT_P_CLEAR

clear the pointer of pattern table for DIG ADC1 CTRL
SARADC_XPD_SAR_FORCE

force option to xpd sar blocks
SARADC_WAIT_ARB_CYCLE

wait arbit signal stable after sar_done

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data